General description

The SBC 80/l0A is the member of Intel’s complete line of OEM computer systems which take full advantage of Intel’s LSI technology to provide economical, self-contained computer based solutions for OEM applications. The SBC 80/l0A is a complete computer systems, each on a single 6.75-by-12 inch printed circuit card.

The CPU, system clock, read/write memory, non-volatile read-only-memory,I/O ports and drivers, serial communications interface, bus control logic and drivers all reside on the board. Intel’s powerful S-bit n-channel MOS 8080A CPU, fabricated on a single LSI chip, is the central processor for the SBC 80/10A. The 8080A contains six 8-bit general purpose registers and an accumulator. The six general purpose registers may be addressed individually or in pairs providing both single and double precision operators. The 8080A has a l6-bit program counter which allows direct addressing of up to 64K of memory. An external stack, located within any portion of memory, may be used as a last in/first out stack to store and retrieve the contents of the program counter, flags, accumulator and all of the six general purpose registers. A sixteen bit stack pointer controls the addressing of this external stack. This stack provides almost unlimited subroutine nesting. Sixteen-line address and eight-line bi-directional data busses are used to facilitate easy interface to memory and I/O.

The powerful 8080A instruction set allows the user to write efficient programs in a minimum amount of time. The accumulator group instructions include arithmetic and logical operators with direct, register direct, and immediate addressing modes. Move, load, and store instruction groups provide the ability to move either 8 or 16 bits of data between memory, the six working registers and the accumulator using all addressing modes. The ability to branch to different portions of a program is provided with jump, jump conditional, and computed jumps. The ability to conditionally and unconditionally call to and return from subroutines is provided. The RESTART (or single byte call instruction) is used for interrupt operation. Double precision operators such as stack manipulation and double add instructions extend both the arithmetic and interrupt handling capability of the 8080A. The ability to increment and decrement memory, the six general registers, and the accumulator is provided as well as extended increment and decrement instructions to operate on the register pairs and stack pointer.

The SBC 80/10A contains IK 8-bit words of read/write memory using Intel’s 8102 Low Power Static RAMs. Sockets for up to 4K or 8K words of non-volatile read-only memory are provided on the SBC 80/10A. Up to 4K of read-only memory may be added in 1K byte increments using Intel’s 8708 Erasable and Electrically Reprogrammable ROMs (EPROMs), Intel’s 2758 Erasable and Electrically Reprogrammable ROMs (EPROMs), or Intel’s 8308 Metal Masked ROMs. Optionally up to 8K words of read-only memory may be added in 2K byte increments using Intel’s 2716 Erasable and Electrically Reprogrammable ROMs (EPROMs) or Intel’s 2316E Metal Masked ROMs.

The SBC 80/10 contains 48 programmable parallel I/O lines implemented using two Intel 8255 Programmable Peripheral Interface devices. The software is used to configure the I/O lines in combinations of uni-directional input/output, and bidirectional ports. Therefore, the I/O interface :nay be customized to meet specifIed peripheral requirements. In order to take full advantage of the large number of possible I/O configurations, sockets are provided for interchangable I/O line drivers and terminators. Hence, the flexibility of the I/O interface is further enhanced by the capability of selecting the appropriate optional line drivers and terminators for each application.

A programmable serial communications interface using Intel’s 8251 Universal Synchronous/Asynchronous Receiver/Transmitter (USART) is contained on the board. The USART can be programmed by the systems software to provide virtually any serial data transmission technique presently in use (including IBM Bi-Sync). The mode of operation (synchronous or asynchronous), data format, control character format, parity, and asynchronous serial transmission rate are under program control.

The 8251 provides full duplex, double buffered transmission and receive capability. Parity, overrun, and framing error detection are all incorporated in the USART. The inclusion of jumper selectable teletype, or RS232C compatible interfaces on the board in conjunction with the USART provide a direct interface to a teletype, CRT, RS232C compatible devices, and asynchronous and synchronous modems.

A single-level interrupt may originate from anyone of six sources including the USART, Programmable I/O interface, and two user designated interrupt request lines. When an interrupt request is recognized, a RESTART 7 instruction is generated. The processor responds by suspending program execution and executing a user defined interrupt service routine originating at location 3816.

Memory and I/O expansion may be achieved using standard Intel boards. Memory may be expanded to 65,536 bytes b} adding user specified combinations of SBC 016 16K byte RAM board, SBC 406 6K byte and SBC 416 16K byte PROM boards. Input/output capacity may’ be expanded in increments of 4 input ports and 4 output ports using SBC 508 Input/Output boards. Expandable backplanes and cardcages are available to
support multi-board systems.

The development cycle of SBC 80/10 based OEM products may be significantly reduced using the Intellec Microcomputer Development System. The resident assembler, text editor, and system monitor greatly simplify the design, development, and debug of SBC 80/10 based system software.

A unique In-Circuit Emulator (ICE-80) option provides the capability of executing and debugging OEM system software directly on the SBC 80/10.

Intel’s high-level language, PL/M, can be used to significantly decrease the time required to develop OEM system software.

Electronics diagrams


The SBC 80/10’s system bus structure permits interfacing to one other Multibus-Compatible Master module. This interface is accomplished using the serial priority scheme using the Intel SBC 604 Cardcage/Backplane.

The SBC 80/10 does not provide the Bus Priority Request Out (BPRO/) signal and therefore, the SBC 80/10 can only be used with one other Multibus master. For these configurations, the SBC 80/10 must always have lower priority than the other Multibus master and a wire must be added from the master’s BREQ/ pin (pin 18) to the SBC 80/10 BPRN pin (pin 15). The SBC 80/10 acquires control of the Multibus whenever BREQ/ generated by the Diskette Controller is in the high state. This occurs whenever the Diskette Controller is not using the Multibus. Similarly BREQ/ is driven to the low state when the Diskette Controller acquires control of the Multibus disabling the SBC 80/10 from accessing the Multibus.
For a detailed description of Multibus interfacing refer to the Intel Multibus Interfacing Application Note (AP-28).